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NB3N551 3.3 V / 5.0 V Ultra-Low Skew 1:4 Clock Fanout Buffer
Description
The NB3N551 is a low skew 1-to 4 clock fanout buffer, designed for clock distribution in mind. The NB3N551 specifically guarantees low output-to-output skew. Optimal design, layout and processing minimize skew within a device and from device to device. The output enable (OE) pin three-states the outputs when low.
Features
http://onsemi.com MARKING DIAGRAMS*
8 8 1 3N551 A L Y W G SOIC-8 D SUFFIX CASE 751 1 = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package 6K MG G 1 4 8 7 6 5 OE VDD GND Q4 Shipping 98 Units/Rail 2500/Tape & Reel 1000/Tape & Reel 3N551 ALYW G
* * * * * * * *
Input/Output Clock Frequency up to 180 MHz Low Skew Outputs (50 ps typical) Output goes to Three-State Mode via OE Operating Range: VDD = 3.0 V to 5.5 V Ideal for Networking Clocks Packaged in 8-pin SOIC Industrial Temperature Range These are Pb-Free Devices
1 Q1 Q2 CLK Q3 Q4
DFN8 MN SUFFIX CASE 506AA 6K M G
= Specific Device Code = Date Code = Pb-Free Package
(Note: Microdot may be in either location) *For additional marking information, refer to Application Note AND8002/D.
PIN CONNECTIONS
ICLK Q1 Q2 Q3 1 2 3 4
OE
Figure 1. Block Diagram
ORDERING INFORMATION
Device NB3N551DG NB3N551DR2G NB3N551MNR4G Package SOIC-8 (Pb-Free) SOIC-8 (Pb-Free) DFN-8 (Pb-Free)
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D.
(c) Semiconductor Components Industries, LLC, 2006
October, 2006 - Rev. 2
1
Publication Order Number: NB3N551/D
NB3N551
OE 0 1 Function Disable Enable
Table 1. OE, Output Enable Function PIN DESCRIPTION
Pin # 1 2 3 4 5 6 7 8 Name ICLK Q1 Q2 Q3 Q4 GND VDD OE Type (LV)CMOS/(LV)TTL Input (LV)CMOS/(LV)TTL Output (LV)CMOS/(LV)TTL Output (LV)CMOS/(LV)TTL Output (LV)CMOS/(LV)TTL Output Power Power (LV)CMOS/(LV)TTL Input Description Clock Input. Internal pull-up resistor. Clock Output 1 Clock Output 2 Clock Output 3 Clock Output 4 Negative supply voltage; Connect to ground, 0 V Positive supply voltage (3.0 V to 5.5 V) Output Enable for the clock outputs. Outputs are enabled when HIGH or when left open; OE pin has internal pull-up resistor. Three-states outputs when LOW.
MAXIMUM RATINGS
Symbol VDD VI/VO TA Tstg qJA qJC qJA Parameter Positive Power Supply Input/Output Voltage Operating Temperature Range, Industrial Storage Temperature Range Thermal Resistance (Junction-to-Ambient) Thermal Resistance (Junction-to-Case) Thermal Resistance (Junction-to-Ambient) Condition 1 GND = 0 V t 1.5 ns - - 0 LFPM 500 LFPM (Note 1) 0 LFPM 500 LFPM Condition 2 - - - - SOIC-8 SOIC-8 DFN-8 DFN-8 Rating 7.0 GND-1.5 VI/VO VDD+1.5 -40 to +85 -65 to +150 190 130 41 to 44 129 84 Units V V _C _C _C/W _C/W _C/W _C/W
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. JEDEC standard multilayer board - 2S2P (2 signal, 2 power)
ATTRIBUTES
Characteristic ESD Protection Human Body Model Machine Model Value > 4 kV > 200 V Level 1 UL-94 code V-0 @ 0.125 in 531 Devices
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 2) Flammability Rating Transistor Count Meets or Exceeds JEDEC Standard EIA/JESD78 IC Latchup Test Oxygen Index: 28 to 34
2. For additional Moisture Sensitivity information, refer to Application Note AND8003/D.
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NB3N551
DC CHARACTERISTICS (VDD = 3.0 V to 3.6 V, GND = 0 V, TA = -40C to +85C) (Note 3)
Symbol IDD VOH VOL VOH VIH, ICLK VIL, ICLK VIH, OE VIL, OE ZO RPU CIN IOS Characteristic Power Supply Current @ 135 MHz, No Load, VDD = 3.3 V Output HIGH Voltage - IOH = -25 mA, VDD = 3.3 V Output LOW Voltage - IOL = 25 mA Output HIGH Voltage - IOH = -12 mA (CMOS level) Input HIGH Voltage, ICLK Input LOW Voltage, ICLK Input HIGH Voltage, OE Input LOW Voltage, OE Nominal Output Impedance Input Pull-up Resistor, OE Input Capacitance, OE Short Circuit Current Min - 2.4 - VDD - 0.4 (VDD/2)+0.7 - 2.0 0 - - - - Typ 20 - - - - - - - 20 220 5.0 50 Max 40 - 0.4 - 3.8 (VDD/2)-0.7 VDD 0.8 - - - - Unit mA V V V V V V V W kW pF mA
DC CHARACTERISTICS (VDD = 4.5 V to 5.5 V, GND = 0 V, TA = -40C to +85C) (Note 3)
Symbol IDD VOH VOL VOH VIH, ICLK VIL, ICLK VIH, OE VIL, OE ZO RPU CIN IOS Characteristic Power Supply Current @ 135 MHz, No Load, VDD = 5.0 V Output HIGH Voltage - IOH = -35 mA Output LOW Voltage - IOL = 35 mA Output HIGH Voltage - IOH = -12 mA (CMOS level) Input HIGH Voltage, ICLK Input LOW Voltage, ICLK Input HIGH Voltage, OE Input LOW Voltage, OE Nominal Output Impedance Input Pull-up Resistor, OE Input Capacitance, OE Short Circuit Current Min - 2.4 - VDD - 0.4 (VDD/2) + 1 - 2.0 0 - - - - Typ 50 - - - - - - - 20 220 5.0 80 Max 95 - 0.4 - 5.5 (VDD/2) - 1 VDD 0.8 - - - - Unit mA V V V V V V V W kW pF mA
AC CHARACTERISTICS (VDD = 3.0 V to 5.5 V, GND = 0 V, TA = -40C to +85C) (Note 3)
Symbol fin tjitter (pd) tr/tf tpd tskew Input Frequency Period Jitter (RMS, 1) Output rise and fall times; 0.8 V to 2.0 V Propagation Delay, CLK to Qn, 0 - 180 MHz, (Note 4) Output-to-output skew; (Note 5) Characteristic Min - - - 1.5 - Typ - 2.0 0.5 3.0 50 Max 180 - 1.0 6.0 160 Unit MHz ps ns ns ps
3. Outputs loaded with external RL = 33-W series resistor and CL = 15 pF to GND for proper operation. Duty cycle out = duty in. A 0.01 mF decoupling capacitor should be connected between VDD and GND. A 33 W series terminating resistor may be used on each clock output if the trace is longer than 1 inch. 4. Measured with rail-to-rail input clock. 5. Measured on rising edges at VDD / 2.
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NB3N551
PACKAGE DIMENSIONS
SOIC-8 NB CASE 751-07 ISSUE AG
-X-
A
8 5
B
1
S
4
0.25 (0.010)
M
Y
M
-Y- G
K
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751-01 THRU 751-06 ARE OBSOLETE. NEW STANDARD IS 751-07. MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0_ 8_ 0.010 0.020 0.228 0.244
C -Z- H D 0.25 (0.010)
M SEATING PLANE
N
X 45 _
0.10 (0.004)
M
J
ZY
S
X
S
DIM A B C D G H J K M N S
SOLDERING FOOTPRINT*
1.52 0.060
7.0 0.275
4.0 0.155
0.6 0.024
1.270 0.050
SCALE 6:1 mm inches
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
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NB3N551
PACKAGE DIMENSIONS
DFN8 CASE 506AA-01 ISSUE D
D A B
PIN ONE REFERENCE NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994 . 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. DIM A A1 A3 b D D2 E E2 e K L MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.20 REF 0.20 0.30 2.00 BSC 1.10 1.30 2.00 BSC 0.70 0.90 0.50 BSC 0.20 --- 0.25 0.35
E
2X
0.10 C
2X
0.10 C
0.10 C
8X
0.08 C
SEATING PLANE
A1
e/2
1 8X 4
L
K
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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CCC CCC CCC CCC
8
TOP VIEW
A (A3) C e
SIDE VIEW D2
E2
5 8X
b
0.10 C A B 0.05 C
NOTE 3
BOTTOM VIEW
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NB3N551/D

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